Verilog_World

Wednesday, 9 November 2016

11. Verilog code for 8:1 Multiplexer( Different moduling style).

// Verilog code for 8:1 Multiplexer using Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 21:33:27 11/08/2016
// Designer Name: Madhu Krishna
// Module Name: mux8_1_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux8_1_code(input_d0,
input_d1,
input_d2,
input_d3,
input_d4,
input_d5,
input_d6,
input_d7,
sel_0,
sel_1,
sel_2,
output_y);
// INPUTS
input input_d0;
input input_d1;
input input_d2;
input input_d3;
input input_d4;
input input_d5;
input input_d6;
input input_d7;
input sel_0;
input sel_1;
input sel_2;

// OUTPUT
output output_y;
wire [10:0] mux_comb_out ;

// Declaration using data flow

assign mux_comb_out[0] = ~( sel_0);
assign mux_comb_out[1] = ~( sel_1);
assign mux_comb_out[2] = ~( sel_2);
assign mux_comb_out[3] = (input_d0 & mux_comb_out[2] & mux_comb_out[1] & mux_comb_out[0]);
assign mux_comb_out[4] = (input_d1 & mux_comb_out[2] & mux_comb_out[1] & sel_0);
assign mux_comb_out[5] = (input_d2 & mux_comb_out[2] & sel_1 & mux_comb_out[0]);
assign mux_comb_out[6] = (input_d3 & mux_comb_out[2] & sel_1 & sel_0);
assign mux_comb_out[7] = (input_d4 & sel_2 & mux_comb_out[1] & mux_comb_out[0]);
assign mux_comb_out[8] = (input_d5 & sel_2 & mux_comb_out[1] & sel_0);
assign mux_comb_out[9] = (input_d6 & sel_2 & sel_1 & mux_comb_out[0]);
assign mux_comb_out[10] = (input_d7 & sel_2 & sel_1 & sel_0);
assign output_y = (mux_comb_out[3] | mux_comb_out[4] | mux_comb_out[5] | mux_comb_out[6] | mux_comb_out[7] |mux_comb_out[8] | mux_comb_out[9] | mux_comb_out[10]);
endmodule

------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 8:1 Multiplexer using strucutural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 21:33:27 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux8_1_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux8_1_str( input_d0,

input_d1,

input_d2,

input_d3,

input_d4,

input_d5,

input_d6,

input_d7,

sel_0,

sel_1,

sel_2,

output_y

);

// INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input input_d4;

input input_d5;

input input_d6;

input input_d7;

input sel_0;

input sel_1;

input sel_2;

// OUTPUT

output output_y;

wire [10:0] mux_comb_out ;

// NOT Gate Instantiation Template

not_gate_code U_NOT_GATE1 (

.input_a(sel_0),

.output_y(mux_comb_out[0])

);

not_gate_code U_NOT_GATE2 (

.input_a(sel_1),

.output_y(mux_comb_out[1])

);

not_gate_code U_NOT_GATE3 (

.input_a(sel_2),

.output_y(mux_comb_out[2])

);

// AND Gate Instantiation Template

and_gate4_code U_AND_GATE1 (

.input_a(input_d0),

.input_b(mux_comb_out[0]),

.input_c(mux_comb_out[1]),

.input_d(mux_comb_out[2]),

.output_y(mux_comb_out[3])

);

and_gate4_code U_AND_GATE2 (

.input_a(input_d1),

.input_b(sel_0),

.input_c(mux_comb_out[1]),

.input_d(mux_comb_out[2]),

.output_y(mux_comb_out[4])

);

and_gate4_code U_AND_GATE3 (

.input_a(input_d2),

.input_b(mux_comb_out[0]),

.input_c(sel_1),

.input_d(mux_comb_out[2]),

.output_y(mux_comb_out[5])

);

and_gate4_code U_AND_GATE4 (

.input_a(input_d3),

.input_b(sel_0),

.input_c(sel_1),

.input_d(mux_comb_out[2]),

.output_y(mux_comb_out[6])

);

and_gate4_code U_AND_GATE5 (

.input_a(input_d4),

.input_b(mux_comb_out[0]),

.input_c(mux_comb_out[1]),

.input_d(sel_2),

.output_y(mux_comb_out[7])

);

and_gate4_code U_AND_GATE6 (

.input_a(input_d5),

.input_b(sel_0),

.input_c(mux_comb_out[1]),

.input_d(sel_2),

.output_y(mux_comb_out[8])

);

and_gate4_code U_AND_GATE7 (

.input_a(input_d6),

.input_b(mux_comb_out[0]),

.input_c(sel_1),

.input_d(sel_2),

.output_y(mux_comb_out[9])

);

and_gate4_code U_AND_GATE8 (

.input_a(input_d6),

.input_b(sel_0),

.input_c(sel_1),

.input_d(sel_2),

.output_y(mux_comb_out[10])

);

// OR Gate Instantiation Template

or_gate8_code U_OR_GATE (

.input_a(mux_comb_out[3]),

.input_b(mux_comb_out[4]),

.input_c(mux_comb_out[5]),

.input_d(mux_comb_out[6]),

.input_e(mux_comb_out[7]),

.input_f(mux_comb_out[8]),

.input_g(mux_comb_out[9]),

.input_h(mux_comb_out[10]),

.output_y(output_y)

);

endmodule

// 8 Input OR Gate is required for above structural design

// Verilog code for 8 input or gate

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 23:19:15 11/08/2016

// Designer Name: Madhu krishna

// Module Name: or_gate8_code

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module or_gate8_code(input_a,

input_b,

input_c,

input_d,

input_e,

input_f,

input_g,

input_h,

output_y);

// INPUTS

input input_a;

input input_b;

input input_c;

input input_d;

input input_e;

input input_f;

input input_g;

input input_h;

// OUTPUT

output output_y;

//Declaration of 8 input and gate

endmodule

---------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 8:1 Multiplexer using behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 21:33:27 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux8_1_beh

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux8_1_beh( input_d0,

input_d1,

input_d2,

input_d3,

input_d4,

input_d5,

input_d6,

input_d7,

sel_0,

sel_1,

sel_2,

output_y );

// INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input input_d4;

input input_d5;

input input_d6;

input input_d7;

input sel_0;

input sel_1;

input sel_2;

// OUTPUT

output output_y;

wire [2:0] con_out;

reg output_y;

// Declaration 8:1 Multiplexer

assign con_out = {sel_2, sel_1, sel_0};

always @(*) begin

if(con_out == 3'b000) begin

output_y <= input_d0;

end else if(con_out == 3'b001) begin

output_y <= input_d1;

end else if(con_out == 3'b010) begin

output_y <= input_d2;

end else if(con_out == 3'b011) begin

output_y <= input_d3;

end else if(con_out == 3'b100) begin

output_y <= input_d4;

end else if(con_out == 3'b101) begin

output_y <= input_d5;

end else if(con_out == 3'b110) begin

output_y <= input_d6;

end else begin

output_y <= input_d7;

end

endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 8:1 Multiplexer using behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 21:33:27 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux8_1_beh1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux8_1_beh1( input_d0,

input_d1,

input_d2,

input_d3,

input_d4,

input_d5,

input_d6,

input_d7,

sel_0,

sel_1,

sel_2,

output_ );

// INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input input_d4;

input input_d5;

input input_d6;

input input_d7;

input sel_0;

input sel_1;

input sel_2;

// OUTPUT

output output_y;

wire [2:0] con_out;

reg output_y;

// Declaration 8:1 Multiplexer using case

assign con_out = {sel_2 ,sel_1,sel_0};

always @(*) begin

case (con_out)

3'b000: output_y = input_d0;

3'b001: output_y = input_d1;

3'b010: output_y = input_d2;

3'b011: output_y = input_d3;

3'b100: output_y = input_d4;

3'b101: output_y = input_d5;

3'b110: output_y = input_d6;

3'b111: output_y = input_d7;

default: output_y = 1'b0;

endcase

end

endmodule

--------------------------------------------------------------------------------------------------------------------------------------------------

Tuesday, 8 November 2016

10. Verilog code for 4:1 Multiplexer( Different moduling style).

// Verilog code for 4:1 Multiplexer using Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 17:36:36 11/08/2016
// Designer Name: Madhu Krishna
// Module Name: mux4_1_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux4_1_code(input_d0,
input_d1,
input_d2,
input_d3,
sel_0,
sel_1,
output_y);
//INPUTS
input input_d0;
input input_d1;
input input_d2;
input input_d3;
input sel_0;
input sel_1;

//OUTPUT
output output_y;
wire [7:0]con_lin;
//Declaration of 4:1 Mux
assign con_lin[0] = (~sel_0);
assign con_lin[1] = (~sel_1);
assign con_lin[2] = (con_lin[0] & con_lin[1] & input_d0);
assign con_lin[3] = (sel_0 & con_lin[1] & input_d1);
assign con_lin[4] = (con_lin[0] & sel_1 & input_d2);
assign con_lin[5] = (sel_0 & sel_1 & input_d3);
assign con_lin[6] = (con_lin[2] | con_lin[3]);
assign con_lin[7] = (con_lin[4] | con_lin[5]);
assign output_y = (con_lin[6] | con_lin[7]);
endmodule

------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 4:1 Multiplexer using structural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_str (input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [7:0]con_lin;

// NOT Gate Instantiation Template

not_gate_code U_NOT_GATE1 (

.input_a(sel_0),

.output_y(con_lin[0])

);

not_gate_code U_NOT_GATE2 (

.input_a(sel_1),

.output_y(con_lin[1])

);

// AND Gate Instantiation Template

and_gate_3in U_AND_GATE1(

.input_a(con_lin[1]),

.input_b(con_lin[0]),

.input_c(input_d0),

.output_y(con_lin[2])

);

and_gate_3in U_AND_GATE2 (

.input_a(con_lin[1]),

.input_b(sel_0),

.input_c(input_d1),

.output_y(con_lin[3])

);

and_gate_3in U_AND_GATE3 (

.input_a(sel_1),

.input_b(con_lin[0]),

.input_c(input_d2),

.output_y(con_lin[4])

);

and_gate_3in U_AND_GATE4 (

.input_a(sel_1),

.input_b(sel_0),

.input_c(input_d3),

.output_y(con_lin[5])

);

// OR Gate Instantiation Template

or_gate_code U_OR_GATE1 (

.input_a(con_lin[2]),

.input_b(con_lin[3]),

.output_y(con_lin[6])

);

or_gate_code U_OR_GATE2 (

.input_a(con_lin[4]),

.input_b(con_lin[5]),

.output_y(con_lin[7])

);

or_gate_code U_OR_GATE3(

.input_a(con_lin[6]),

.input_b(con_lin[7]),

.output_y(output_y)

);

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------

//Verilog code for 4:1 Multiplexer using behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_beh1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_beh1(input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [1:0]con_out;

reg output_y;

// Decalration using if and else if

assign con_out = {sel_1 ,sel_0};

always @(*) begin

if (con_out == 2'b00) begin

output_y <= input_d0;

end else if (con_out == 2'b01) begin

output_y <= input_d1;

end else if (con_out == 2'b10) begin

output_y <= input_d2;

end else begin

output_y <= input_d3;

end

endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------

//Verilog code for 4:1 Multiplexer using behavioural (case)

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_beh2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_beh2(input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [1:0]con_out;

reg output_y;

// Decalration using case

assign con_out = {sel_1 ,sel_0};

always @(*) begin

case(con_out)

2'b00: output_y = input_d0;

2'b01: output_y = input_d1;

2'b10: output_y = input_d2;

2'b11: output_y = input_d3;

endcase

end

endmodule

-----------------------------------------------------------------------------------------------------------------------------------------------

9. Verilog code for 2:1 Multiplexer( Different moduling style).

// Verilog code for 2:1 Multiplexers Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 12:52:06 11/08/2016
// Designer Name: Madhu Krishna
// Module Name: mux2_1_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux2_1_code(input_a,
input_b,
sel_0,
output_y);

// INPUTS
input input_a;
input input_b;
input sel_0;

// OUTPUT
output output_y;

//Declaration of mux2:1

assign output_y = ((~sel_0)& (input_a))| (sel_0 & input_b);

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 2:1 Multiplexers structural.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 12:52:06 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux2_1_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux2_1_str(input_a,

input_b,

sel_0,

output_y);

// INPUTS

input input_a;

input input_b;

input sel_0;

// OUTPUT

output output_y;

wire [2:0] con_out;

// NOT GATE Instantiation Template

not_gate_code U_NOT_GATE (

.input_a(sel_0),

.output_y(con_out[0])

);

// AND GATE Instantiation Template

and_gate_code U_AND_GATE1 (

.input_a(input_a),

.input_b(con_out[0]),

.output_y(con_out[1])

);

// AND GATE Instantiation Template

and_gate_code U_AND_GATE2 (

.input_a(sel_0),

.input_b(input_b),

.output_y(con_out[2])

);

// OR GATE Instantiation Template

or_gate_code U_OR_GATE1 (

.input_a(con_out[1]),

.input_b(con_out[2]),

.output_y(output_y)

);

endmodule

------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 2:1 Multiplexers behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 12:52:06 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux2_1_beh

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux2_1_beh(input_a,

input_b,

sel_0,

output_y);

// INPUTS

input input_a;

input input_b;

input sel_0;

// OUTPUT

output output_y;

reg output_y;

//Declaration of mux2:1

always @ (*) begin

if(sel_0 == 1'b0) begin

output_y <= input_a;

end else begin

output_y <= input_b;

end

endmodule

------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 2:1 Multiplexers behavioural using case

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 12:52:06 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux2_1_beh1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux2_1_beh1(input_a,

input_b,

sel_0,

output_y);

// INPUTS

input input_a;

input input_b;

input sel_0;

// OUTPUT

output output_y;

reg output_y;

//Declaration of mux2:1

always @(*) begin

case(sel_0)

1'b0: output_y = input_a;

1'b1: output_y = input_b;

endcase

end

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------

8. Verilog code for Full subtractor ( Different moduling style).

// Verilog code for Full Subtractor Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 10:18:07 11/08/2016
// Designer Name: Madhu Krishna
// Module Name: full_sub_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module full_sub_code( input_a,
input_b,
input_cin,
diff,
bo);

// INPUTS
input input_a;
input input_b;
input input_cin;

// OUTPUT
output diff;
output bo;

//Declaration of Full Subtractor

assign diff = (input_a ^ input_b ^ input_cin);
assign bo = (~(input_a ^ input_b) & input_cin)| (~input_a & input_b);

endmodule

----------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Full subtractor structural,

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 11:00:30 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: full_sub_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module full_sub_str( input_a,

input_b,

input_cin,

diff,

bo);

// INPUTS

input input_a;

input input_b;

input input_cin;

// OUTPUT

output diff;

output bo;

wire [4:0] con_lin;

// NOT Gate Instantiation Template

not_gate_code U_NOT_GATE1 (

.input_a(input_a),

.output_y(con_lin[0])

);

// XOR Gate Instantiation Template

xor_gate_code U_XOR_GATE1 (

.input_a(input_a),

.input_b(input_b),

.output_y(con_lin[1])

);

// XOR Gate Instantiation Template

xor_gate_code U_XOR_GATE2 (

.input_a(con_lin[1]),

.input_b(input_cin),

.output_y(diff)

);

// Not Gate Instantiation Template

not_gate_code U_NOT_GATE2 (

.input_a(con_lin[1]),

.output_y(con_lin[2])

);

// AND Gate Instantiation Template

and_gate_beh U_AND_GATE1 (

.input_a(con_lin[2]),

.input_b(input_cin),

.output_y(con_lin[3])

);

// AND Gate Instantiation Template

and_gate_beh U_AND_GATE2 (

.input_a(con_lin[0]),

.input_b(input_b),

.output_y(con_lin[4])

);

// OR Gate Instantiation Template

or_gate_code U_OR_GATE1 (

.input_a(con_lin[3]),

.input_b(con_lin[4]),

.output_y(bo)

);

endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Full subtractor using if and else if

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 11:42:27 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: full_sub_beh1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module full_sub_beh1( input_a,

input_b,

input_cin,

diff,

bo);

// INPUTS

input input_a;

input input_b;

input input_cin;

// OUTPUTS

output diff;

output bo;

reg diff;

reg bo;

wire [2:0]con_out;

// Declaration of behavioural style

assign con_out ={input_cin, input_b, input_a};

always @(*) begin

if (con_out == 3'b000) begin

diff <= 1'b0;

bo <= 1'b0;

end else if (con_out == 3'b001) begin

diff <= 1'b1;

bo < = 1'b1;

end else if (con_out == 3'b010) begin

diff <= 1'b1;

bo <= 1'b1;

end else if (con_out == 3'b011) begin

diff <= 1'b0;

bo <= 1'b1;

end else if (con_out == 3'b100) begin

diff <= 1'b1;

bo <= 1'b0;

end else if (con_out == 3'b101) begin

diff <= 1'b0;

bo <=1'b0;

end else if (con_out == 3'b110) begin

diff <= 1'b0;

bo <= 1'b0;

end else begin

diff <= 1'b1;

bo <= 1'b1;

end

endmodule

------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Full subtractor using case

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 11:42:27 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: full_sub_beh2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module full_sub_beh2( input_a,

input_b,

input_cin,

diff,

bo);

// INPUTS

input input_a;

input input_b;

input input_cin;

// OUTPUTS

output diff;

output bo;

reg diff;

reg bo;

wire [2:0]con_out;

// Declaration of behavioural style

assign con_out ={input_cin, input_b, input_a};

always @(*) begin

case(con_out)

3'b000:begin

diff = 1'b0;

bo = 1'b0;

end

3'b001:begin

diff = 1'b1;

bo = 1'b1;

end

3'b010:begin

diff = 1'b1;

bo = 1'b1;

end

3'b011:begin

diff = 1'b0;

bo = 1'b1;

end

3'b100:begin

diff = 1'b1;

bo = 1'b0;

end

3'b101:begin

diff = 1'b0;

bo = 1'b0;

end

3'b110:begin

diff = 1'b0;

bo = 1'b0;

end

3'b111:begin

diff = 1'b1;

bo = 1'b1;

end

endcase

end

endmodule

------------------------------------------------------------------------------------------------------------------------

Monday, 7 November 2016

7. Verilog code for Half subtractor ( Different moduling style).

// Verilog code for Half Subtractor
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 15:25:35 11/07/2016
// Designer Name: Madhu Krishna
// Module Name: half_sub
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module half_sub( input_a,
input_b,
diff,
bo);

// INPUTS
input input_a;
input input_b;

// OUTPUT
output diff;
output bo;

//Declaration of Half_sub

assign diff = input_a ^ input_b;
assign bo = (~(input_a) & input_b);
endmodule

-------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Half Subtractor

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 15:43:44 11/07/2016

// Designer Name: Madhu Krishna

// Module Name: half_sub_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module half_sub_str( input_a,

input_b,

diff,

bo);

// INPUTS

input input_a;

input input_b;

// OUTPUTS

output diff;

output bo;

wire con_lin;

// NOT gate Instantiation Template

not_gate_code U_NOT_GATE(

.input_a(input_a),

.output_y(con_lin)

);

// XOR gate Instantiation Template

xor_gate_beh U_XOR_GATE (

.input_a(input_a),

.input_b(input_b),

.output_y(diff)

);

// AND gate Instantiation Template

and_gate_code U_AND_GATE (

.input_a(con_lin),

.input_b(input_b),

.output_y(bo)

);

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code Half subtractor

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 16:06:07 11/07/2016

// Designer Name: Madhu Krishna

// Module Name: half_sub_beh

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module half_sub_beh( input_a,

input_b,

diff,

bo);

// INPUTS

input input_a;

input input_b;

// OUTPUTS

output diff;

output bo;

reg diff;

reg bo;

wire [1:0]con_out;

// Declaration of half sub

assign con_out = {input_a,input_b};

always @(*) begin

if(con_out == 2'b00) begin

diff <= 1'b0;

bo <= 1'b0;

end else if(con_out == 2'b01) begin

diff <= 1'b1;

bo <= 1'b1;

end else if(con_out == 2'b10)begin

diff <= 1'b1;

bo <= 1'b0;

end else begin

diff <= 1'b0;

bo <= 1'b0;

end

endmodule

------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Half Subtractor

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 16:32:16 11/07/2016

// Designer Name: Madhu krishna

// Module Name: half_sub_beh2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module half_sub_beh2( input_a,

input_b,

diff,

bo);

// INPUTS

input input_a;

input input_b;

// OUTPUTS

output diff;

output bo;

reg diff;

reg bo;

wire [1:0]con_out;

// Half subtractor code using case

assign con_out = {input_a,input_b};

always @(*)begin

case (con_out)

2'b00 : begin

diff <= 1'b0;

bo <= 1'b0;

end

2'b01 : begin

diff <= 1'b1;

bo <= 1'b1;

end

2'b10 : begin

diff <= 1'b1;

bo <= 1'b0;

end

2'b11 : begin

diff <= 1'b0;

bo <= 1'b0;

end

endcase

end

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------

6. Verilog code for Full Adder ( Different moduling style).

//Verilog code for FULL ADDER
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED BLUE
// Engineer:
//
// Create Date: 22:34:33 11/04/2016
// Designer Name: Madhu Krishna
// Module Name: full_adder_code
// Project Name
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module full_adder_code(input_A,
input_B,
input_Cin,
sum,
carry);
//INPUTS

input input_A;
input input_B;
input input_Cin;

//OUPUTS

output sum;
output carry;

reg sum;
reg carry;

//Declaring the sum and carry value

initial begin
assign sum = (input_A)^(input_B)^(input_Cin);
assign carry = ((input_A) & (input_B))|((input_B) & (input_Cin))|((input_Cin)|(input_A));
end
endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Full Adder structural
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED BLUE
// Engineer:
//
// Create Date: 12:16:00 11/07/2016
// Design Name: Madhu Krishna
// Module Name: full_adder_str
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module full_adder_str( input_a,
input_b,
input_cin,
sum,
carry);

// INPUTS
input input_a;
input input_b;
input input_cin;

// OUTPUTs

output sum;
output carry;
wire [3:0] con_lin;

// XOR Gate Instantiation Template
xor_gate_3in U_XOR_GATE_3IN (
.input_a(input_a),
.input_b(input_b),
.input_c(input_cin),
.output_y(sum)
);

// AND Gate Instantiation Template
and_gate_beh U_AND_GATE1 (
.input_a(input_a),
.input_b(input_b),
.output_y(con_lin[0])
);

and_gate_beh U_AND_GATE2 (
.input_a(input_a),
.input_b(input_cin),
.output_y(con_lin[1])
);

and_gate_beh U_AND_GATE3 (
.input_a(input_cin),
.input_b(input_a),
.output_y(con_lin[2])
);

// OR Gate Instantiation Template

or_gate_code U_OR_GATE1 (
.input_a(con_lin[0]),
.input_b(con_lin[1]),
.output_y(con_lin[3])
);

or_gate_code U_OR_GATE2 (
.input_a(con_lin[3]),
.input_b(con_lin[2]),
.output_y(carry)
);
endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for FULL ADDER Behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 13:09:06 11/07/2016

// Designer Name: Madhu Krishna

// Module Name: full_adder_beh

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module full_adder_beh( input_a,

input_b,

input_cin,

sum,

carry);

// INPUTS

input input_a;

input input_b;

input input_cin;

// OUTPUTS

output sum;

output carry;

reg sum;

reg carry;

wire [2:0]con_out;

assign con_out = {input_cin,input_b,input_a};

always @(*) begin

if(con_out == 3'b000) begin

sum <= 1'b0;

carry <= 1'b0;

end else if (con_out == 3'b001) begin

sum <= 1'b1;

carry <= 1'b0;

end else if (con_out == 3'b010) begin

sum <= 1'b1;

carry <= 1'b0;

end else if (con_out == 3'b011) begin

sum <= 1'b0;

carry <= 1'b1;

end else if (con_out == 3'b100) begin

sum <= 1'b1;

carry <= 1'b0;

end else if (con_out == 3'b101) begin

sum <= 1'b0;

carry <= 1'b1;

end else if (con_out == 3'b110) begin

sum <= 1'b0;

carry <= 1'b1;

end else begin

sum <=1'b1;

carry <=1'b1;

end

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for Full Adder using case

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-KRISHNA

// Engineer:

// Create Date: 14:39:42 11/07/2016

// Designer Name: Madhu-Krishna

// Module Name: full_adder_beh2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module full_adder_beh2 (input_a,

input_b,

input_cin,

sum,

carry);

// INPUTS

input input_a;

input input_b;

input input_cin;

// OUTPUTS

output sum;

output carry;

reg sum;

reg carry;

wire [2:0] con_out;

assign con_out = {input_cin, input_b, input_a};

always @(*) begin

case (con_out)

3'b000: begin

sum <=1'b0;

carry<=1'b0;

end

3'b001: begin

sum <=1'b1;

carry<=1'b0;

end

3'b010: begin

sum <=1'b1;

carry<=1'b0;

end

3'b011: begin

sum <=1'b0;

carry<=1'b1;

end

3'b100: begin

sum <=1'b1;

carry<=1'b0;

end

3'b101: begin

sum <=1'b0;

carry<=1'b1;

end

3'b110: begin

sum <=1'b0;

carry<=1'b1;

end

3'b111: begin

sum <=1'b1;

carry<=1'b1;

end

endcase

end

endmodule

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------