Verilog_World: 10. Verilog code for 4:1 Multiplexer( Different moduling style).

// Verilog code for 4:1 Multiplexer using Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 17:36:36 11/08/2016
// Designer Name: Madhu Krishna
// Module Name: mux4_1_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux4_1_code(input_d0,
input_d1,
input_d2,
input_d3,
sel_0,
sel_1,
output_y);
//INPUTS
input input_d0;
input input_d1;
input input_d2;
input input_d3;
input sel_0;
input sel_1;

//OUTPUT
output output_y;
wire [7:0]con_lin;
//Declaration of 4:1 Mux
assign con_lin[0] = (~sel_0);
assign con_lin[1] = (~sel_1);
assign con_lin[2] = (con_lin[0] & con_lin[1] & input_d0);
assign con_lin[3] = (sel_0 & con_lin[1] & input_d1);
assign con_lin[4] = (con_lin[0] & sel_1 & input_d2);
assign con_lin[5] = (sel_0 & sel_1 & input_d3);
assign con_lin[6] = (con_lin[2] | con_lin[3]);
assign con_lin[7] = (con_lin[4] | con_lin[5]);
assign output_y = (con_lin[6] | con_lin[7]);
endmodule

------------------------------------------------------------------------------------------------------------------------------------------

// Verilog code for 4:1 Multiplexer using structural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_str

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_str (input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [7:0]con_lin;

// NOT Gate Instantiation Template

not_gate_code U_NOT_GATE1 (

.input_a(sel_0),

.output_y(con_lin[0])

);

not_gate_code U_NOT_GATE2 (

.input_a(sel_1),

.output_y(con_lin[1])

);

// AND Gate Instantiation Template

and_gate_3in U_AND_GATE1(

.input_a(con_lin[1]),

.input_b(con_lin[0]),

.input_c(input_d0),

.output_y(con_lin[2])

);

and_gate_3in U_AND_GATE2 (

.input_a(con_lin[1]),

.input_b(sel_0),

.input_c(input_d1),

.output_y(con_lin[3])

);

and_gate_3in U_AND_GATE3 (

.input_a(sel_1),

.input_b(con_lin[0]),

.input_c(input_d2),

.output_y(con_lin[4])

);

and_gate_3in U_AND_GATE4 (

.input_a(sel_1),

.input_b(sel_0),

.input_c(input_d3),

.output_y(con_lin[5])

);

// OR Gate Instantiation Template

or_gate_code U_OR_GATE1 (

.input_a(con_lin[2]),

.input_b(con_lin[3]),

.output_y(con_lin[6])

);

or_gate_code U_OR_GATE2 (

.input_a(con_lin[4]),

.input_b(con_lin[5]),

.output_y(con_lin[7])

);

or_gate_code U_OR_GATE3(

.input_a(con_lin[6]),

.input_b(con_lin[7]),

.output_y(output_y)

);

endmodule

-------------------------------------------------------------------------------------------------------------------------------------------------

//Verilog code for 4:1 Multiplexer using behavioural

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_beh1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_beh1(input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [1:0]con_out;

reg output_y;

// Decalration using if and else if

assign con_out = {sel_1 ,sel_0};

always @(*) begin

if (con_out == 2'b00) begin

output_y <= input_d0;

end else if (con_out == 2'b01) begin

output_y <= input_d1;

end else if (con_out == 2'b10) begin

output_y <= input_d2;

end else begin

output_y <= input_d3;

end

endmodule

----------------------------------------------------------------------------------------------------------------------------------------------------

//Verilog code for 4:1 Multiplexer using behavioural (case)

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: RED-BLUE

// Engineer:

// Create Date: 17:36:36 11/08/2016

// Designer Name: Madhu Krishna

// Module Name: mux4_1_beh2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module mux4_1_beh2(input_d0,

input_d1,

input_d2,

input_d3,

sel_0,

sel_1,

output_y);

//INPUTS

input input_d0;

input input_d1;

input input_d2;

input input_d3;

input sel_0;

input sel_1;

// OUTPUT

output output_y;

wire [1:0]con_out;

reg output_y;

// Decalration using case

assign con_out = {sel_1 ,sel_0};

always @(*) begin

case(con_out)

2'b00: output_y = input_d0;

2'b01: output_y = input_d1;

2'b10: output_y = input_d2;

2'b11: output_y = input_d3;

endcase

end

endmodule

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Verilog_World

Tuesday, 8 November 2016

10. Verilog code for 4:1 Multiplexer( Different moduling style).

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