// Verilog code for 2-bit Comparator using Dataflow
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_code( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
//OUTPUTS
output agb;
output aeb;
output alb;
//Declaration of 2 bit comparator
assign agb = ((input_a1) & (~input_b1))|((input_a0) & (~input_b0) & (~input_b1)) | ((input_a0) & (~input_b0) & (input_a1));
assign aeb = (~(input_a0 ^ input_b0)) | (~(input_a1 ^input_b1));
assign alb = ((~input_a1 & input_b1) | ((~input_a0) & (~input_a1) &(input_b0)) | ((~input_a0) & (input_b0) & (input_b1)));
endmodule
---------------------------------------------------------------------------------------------------------------------------------------------------------
// Verilog code for 2-bit Comparator using strcutural
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_str
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_str( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
// OUTPUTS
output agb;
output aeb;
output alb;
wire [11:0] com_out;
// NOT Gate Instantiation Template
not_gate_code U_NOT_GATE1 (
.input_a(input_a1),
.output_y(com_out[0])
);
not_gate_code U_NOT_GATE2 (
.input_a(input_a0),
.output_y(com_out[1])
);
not_gate_code U_NOT_GATE3 (
.input_a(input_b1),
.output_y(com_out[2])
);
not_gate_code U_NOT_GATE4 (
.input_a(input_b0),
.output_y(com_out[3])
);
// AND Gate Instantiation Template
and_gate_code U_AND_GATE1 (
.input_a(input_a1),
.input_b(com_out[2]),
.output_y(com_out[4])
);
// 3 in AND Gate Instantiation Template
and_gate_3in U_AND_GATE2 (
.input_a(input_a0),
.input_b(com_out[3]),
.input_c(com_out[2]),
.output_y(com_out[5])
);
and_gate_3in U_AND_GATE3 (
.input_a(input_a0),
.input_b(com_out[3]),
.input_c(input_a1),
.output_y(com_out[6])
);
// 3 in OR Gate Instantiation Template
or_gate_3in U_OR_GATE1 (
.input_a(com_out[4]),
.input_b(com_out[5]),
.input_c(com_out[6]),
.output_y(agb)
);
// 2 in XNOR Gate Instantiation Template
xnor_gate_code U_XNOR_GATE1 (
.input_a(input_a0),
.input_b(input_bo),
.output_y(com_out[7])
);
xnor_gate_code U_XNOR_GATE2 (
.input_a(input_a1),
.input_b(input_b1),
.output_y(com_out[8])
);
and_gate_code U_AND_GATE4 (
.input_a(com_out[7]),
.input_b(com_out[8]),
.output_y(aeb)
);
// AND Gate Instantiation Template
and_gate_code U_AND_GATE5 (
.input_a(com_out[0]),
.input_b(input_b1),
.output_y(com_out[9])
);
// 3 in AND Gate Instantiation Template
and_gate_3in U_AND_GATE6 (
.input_a(com_out[1]),
.input_b(com_out[0]),
.input_c(input_b0),
.output_y(com_out[10])
);
and_gate_3in U_AND_GATE7 (
.input_a(com_out[1]),
.input_b(input_b0),
.input_c(input_b1),
.output_y(com_out[11])
);
// 3 in OR Gate Instantiation Template
or_gate_3in U_OR_GATE2 (
.input_a(com_out[9]),
.input_b(com_out[10]),
.input_c(com_out[11]),
.output_y(alb)
);
endmodule
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
// Verilog code for 2-bit Comparator using behavioral
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_beh1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_beh1( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
// OUTPUTS
output agb;
output aeb;
output alb;
wire [3:0]com_out;
reg agb;
reg aeb;
reg alb;
// Behavioral style using if and else if
assign com_out = {input_a1, input_a0, input_b1, input_b0};
always @(*) begin
if (com_out == 4'b0000) begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end else if (com_out == 4'b0001) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0010) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0011) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0100) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b0101) begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end else if (com_out == 4'b0110) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0111) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b1000) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1001) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1011) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b1100) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1101) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1110) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_code( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
//OUTPUTS
output agb;
output aeb;
output alb;
//Declaration of 2 bit comparator
assign agb = ((input_a1) & (~input_b1))|((input_a0) & (~input_b0) & (~input_b1)) | ((input_a0) & (~input_b0) & (input_a1));
assign aeb = (~(input_a0 ^ input_b0)) | (~(input_a1 ^input_b1));
assign alb = ((~input_a1 & input_b1) | ((~input_a0) & (~input_a1) &(input_b0)) | ((~input_a0) & (input_b0) & (input_b1)));
endmodule
---------------------------------------------------------------------------------------------------------------------------------------------------------
// Verilog code for 2-bit Comparator using strcutural
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_str
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_str( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
// OUTPUTS
output agb;
output aeb;
output alb;
wire [11:0] com_out;
// NOT Gate Instantiation Template
not_gate_code U_NOT_GATE1 (
.input_a(input_a1),
.output_y(com_out[0])
);
not_gate_code U_NOT_GATE2 (
.input_a(input_a0),
.output_y(com_out[1])
);
not_gate_code U_NOT_GATE3 (
.input_a(input_b1),
.output_y(com_out[2])
);
not_gate_code U_NOT_GATE4 (
.input_a(input_b0),
.output_y(com_out[3])
);
// AND Gate Instantiation Template
and_gate_code U_AND_GATE1 (
.input_a(input_a1),
.input_b(com_out[2]),
.output_y(com_out[4])
);
// 3 in AND Gate Instantiation Template
and_gate_3in U_AND_GATE2 (
.input_a(input_a0),
.input_b(com_out[3]),
.input_c(com_out[2]),
.output_y(com_out[5])
);
and_gate_3in U_AND_GATE3 (
.input_a(input_a0),
.input_b(com_out[3]),
.input_c(input_a1),
.output_y(com_out[6])
);
// 3 in OR Gate Instantiation Template
or_gate_3in U_OR_GATE1 (
.input_a(com_out[4]),
.input_b(com_out[5]),
.input_c(com_out[6]),
.output_y(agb)
);
// 2 in XNOR Gate Instantiation Template
xnor_gate_code U_XNOR_GATE1 (
.input_a(input_a0),
.input_b(input_bo),
.output_y(com_out[7])
);
xnor_gate_code U_XNOR_GATE2 (
.input_a(input_a1),
.input_b(input_b1),
.output_y(com_out[8])
);
and_gate_code U_AND_GATE4 (
.input_a(com_out[7]),
.input_b(com_out[8]),
.output_y(aeb)
);
// AND Gate Instantiation Template
and_gate_code U_AND_GATE5 (
.input_a(com_out[0]),
.input_b(input_b1),
.output_y(com_out[9])
);
// 3 in AND Gate Instantiation Template
and_gate_3in U_AND_GATE6 (
.input_a(com_out[1]),
.input_b(com_out[0]),
.input_c(input_b0),
.output_y(com_out[10])
);
and_gate_3in U_AND_GATE7 (
.input_a(com_out[1]),
.input_b(input_b0),
.input_c(input_b1),
.output_y(com_out[11])
);
// 3 in OR Gate Instantiation Template
or_gate_3in U_OR_GATE2 (
.input_a(com_out[9]),
.input_b(com_out[10]),
.input_c(com_out[11]),
.output_y(alb)
);
endmodule
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
// Verilog code for 2-bit Comparator using behavioral
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_beh1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_beh1( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
// OUTPUTS
output agb;
output aeb;
output alb;
wire [3:0]com_out;
reg agb;
reg aeb;
reg alb;
// Behavioral style using if and else if
assign com_out = {input_a1, input_a0, input_b1, input_b0};
always @(*) begin
if (com_out == 4'b0000) begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end else if (com_out == 4'b0001) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0010) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0011) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0100) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b0101) begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end else if (com_out == 4'b0110) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b0111) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b1000) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1001) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1011) begin
agb <= 1'b0;
aeb <= 1'b0;
alb <= 1'b1;
end else if (com_out == 4'b1100) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1101) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else if (com_out == 4'b1110) begin
agb <= 1'b1;
aeb <= 1'b0;
alb <= 1'b0;
end else begin
agb <= 1'b0;
aeb <= 1'b1;
alb <= 1'b0;
end
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------
// Verilog code for 2-bit Comparator using behavioral
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RED-BLUE
// Engineer:
//
// Create Date: 19:03:59 11/10/2016
// Designer Name: Madhu-Krishna
// Module Name: comp_2bit_beh2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_2bit_beh2( input_a0,
input_a1,
input_b0,
input_b1,
agb,
aeb,
alb);
// INPUTS
input input_a0;
input input_a1;
input input_b0;
input input_b1;
// OUTPUTS
output agb;
output aeb;
output alb;
wire [3:0]com_out;
reg agb;
reg aeb;
reg alb;
// Behavioral style using case
assign com_out = {input_a1, input_a0, input_b1, input_b0};
always @(*) begin
case( com_out)
4'b0000:begin
agb = 1'b0;
aeb = 1'b1;
alb = 1'b0;
end
4'b0001:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b0010:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b0011:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b0100:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b0101:begin
agb = 1'b0;
aeb = 1'b1;
alb = 1'b0;
end
4'b0110:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b0111:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b1000:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b1001:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b1011:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b1;
end
4'b1100:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b1101:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b1110:begin
agb = 1'b1;
aeb = 1'b0;
alb = 1'b0;
end
4'b1111:begin
agb = 1'b0;
aeb = 1'b1;
alb = 1'b0;
end
default:begin
agb = 1'b0;
aeb = 1'b0;
alb = 1'b0;
end
endcase
end
endmodule
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
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